1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuit having an N channel MOS (Metal Oxide Semiconductor) field effect transistor, a P channel MOS field effect transistor and a bipolar transistor, and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a BiCMOS circuit has been used as a circuit of semiconductor device, which includes therein a bipolar transistor with large output allowing high-speed operation and a CMOS (Complementary Metal Oxide Semiconductor) transistor with low power dissipation performance allowing high-level integration.
Hereinafter, a structure of a conventional BiCMOS circuit and a manufacturing method thereof will be described with reference to FIGS. 34 to 43. In a conventional method of manufacturing a BiCMOS circuit, a p type underside isolating layer 105, an n type collector buried layer 102 of relatively high concentration, an n type buried layer 103, and a p type buried layer 104 are formed, spaced apart from one another by prescribed distances, substantially at the same depth from the surface of a p type semiconductor substrate 101.
Next, an n type epitaxial layer 106 of relatively low concentration is formed by epitaxial growth in a region from the surface of semiconductor substrate 101 to reach collector buried layer 102, that is to be an active region of a bipolar transistor. Adjacent to n type epitaxial layer 106, an n type collector wall region 108 of relatively high concentration is formed from the surface of semiconductor substrate 101 to collector buried layer 102. In an active region of a P channel MOS (p type Metal Oxide Semiconductor) transistor, an n type well 109 of relatively low concentration is formed from the surface of semiconductor substrate 101 reaching collector buried layer 103.
In an active region of an N channel MOS (n type Metal Oxide Semiconductor) transistor, a p type well 110 of relatively low concentration is formed from the surface of semiconductor substrate 101 to reach p type buried layer 104 of relatively high concentration. A p type isolating region 111 of low concentration is formed from the surface of semiconductor substrate 101 reaching a respective underside isolating layer 105.
Next, isolating oxide films 107e and 107g are formed on the respective surfaces of isolating regions 111 to separately form element forming regions. An isolating oxide film 107f for separating collector wall region 108 from n type epitaxial layer 106, an isolating oxide film 107h for separating n type well 109 from p type well 110, and an isolating oxide film 107i for separating p type well 110 from another region are also formed. Thereafter, on n type epitaxial layer 106, collector wall region 108, n type well 109, and p type well 110, which are to be active regions, oxide films 107b, 107a, 107c, and 107d are formed, respectively, which results in a structure as shown in FIG. 34.
Next, an n type polycrystalline silicon (polysilicon) film doped with phosphorus is deposited on the entire surface of the structure in FIG. 34, with a film thickness of 1500 xc3x85. Thereafter, a tungsten silicide film with a film thickness of 2000 xc3x85 is formed on the polysilicon film. Next, the tungsten silicide film, the polysilicon film, oxide films 107a and 107b, and oxide films 107c and 107d are selectively etched to form, on the surface of n type well 109, a gate electrode 113 consisting of a polysilicon film 113a and a tungsten silicide film 113b and a gate oxide film 112, and to form, on the surface of p type well 110, a gate electrode 115 consisting of a polysilicon film 115a and a tungsten silicide film 115b and a gate oxide film 114. A structure shown in FIG. 35 is thus obtained.
Thereafter, as shown in FIG. 36, a mask 116 is formed to expose p type well 110. An n type impurity 200, e.g., high concentration phosphorus (hereinafter referred to as xe2x80x9cPxe2x80x9d) ions, is then introduced at implant energy of 70 KeV with a dosage of 2xc3x971013 cmxe2x88x922, thereby forming n type source/drain regions 117a and 117b in p type well 110, as shown in FIG. 37. Thereafter, mask 116 is removed and an oxide film is deposited on the entire surface. Etching is then conducted to form sidewall oxide films 119a, 119b and sidewall oxide films 118a, 118b on respective sides of gate electrodes 113 and 115. Thereafter, as shown in FIG. 37, a mask 120 is formed to expose the surface of p type well 110, and an n type impurity 300, e.g., high concentration arsenic (hereinafter referred to as xe2x80x9cAsxe2x80x9d) ions, is introduced at implant energy of 50 KeV with a dosage of 4xc3x971015 cmxe2x88x922. Accordingly, n type source/drain regions 120a and 120b with an LDD (Lightly Doped Drain) structure are formed in p type well 110, as shown in FIG. 38.
Next, as shown in FIG. 38, masks 121a and 121b are formed to expose n type well 109. Thereafter, a p type impurity 400 of high concentration, e.g., boron fluoride (hereinafter referred to as xe2x80x9cBF2xe2x80x9d) ions, is introduced into n type well 109 at implant energy of 40 KeV with a dosage of 4xc3x971015 cmxe2x88x922, as shown in FIG. 38. Accordingly, p type source/drain regions 122a and 122b, as shown in FIG. 39, are formed.
Next, a 2000 xc3x85 thick polysilicon film is deposited on the entire surface, and BF2 ions, for example, are introduced at implant energy of 40 KeV with a dosage of 4xc3x971015 cmxe2x88x922 to form a conductive polysilicon film that is to be a base electrode. In the step of implanting BF2 ions, the BF2 ions that have been transmitted through the polysilicon film are introduced into n type epitaxial layer 106, thereby forming a portion that is to be a p type external base region. Thereafter, a CVD oxide film with a film thickness of 3000 xc3x85 is further deposited to cover the entire surface. The CVD oxide film, the polysilicon film and the upper portion of n type epitaxial layer 106 are then dry etched using a mask, thus opening, as shown in FIG. 39, a region 106a in which an emitter electrode of the bipolar transistor is to be formed. CVD oxide films 123a and 124a, base electrodes 123b and 124b made of polysilicon film, and p type external base regions 126a and 126b are thus formed.
Thereafter, as shown in FIG. 40, a p type impurity 500 of high concentration, e.g., BF2 ion, is introduced at implant energy of 30 KeV with a dosage of 6xc3x971013 cmxe2x88x922 from the emitter opening region into n type epitaxial layer 106, thereby forming a p type intrinsic base region 128, as shown in FIG. 41. Thereafter, a CVD oxide film is formed on the entire surface, and, by framing etching, sidewall oxide films 127a, 127b, 127c, and 127d are formed on respective sides of base electrodes 123b and 124b made of polysilicon film, and of CVD oxide films 123a and 124a. Next, a polysilicon film doped with no impurities is formed on the entire surface with a film thickness of 2000 xc3x85, a high concentration n type impurity, e.g., As ions, is introduced at implant energy of 50 KeV with a dosage of 1xc3x971016 cmxe2x88x922 therein, and then the film is formed into a shape as shown in FIG. 42, which becomes an n type emitter electrode 129. Here, instead of implanting n type impurity ions, a polysilicon film doped with an n type impurity in advance may be formed.
Next, an interlayer oxide film 130 is formed on the entire surface of the structure shown in FIG. 42. In interlayer oxide film 130, contact holes 130a, 130b, 130c, 130d, 130e, 130f and 130g are formed to connect to collector wall region 108, emitter electrode 129, base electrode 124a, p type source/drain regions 122a and 122b, and n type source/drain regions 120a and 120b, respectively. Thereafter, aluminum is filled in contact holes 130a, 130b, 130c, 130d, 130e, 130f and 130g, and also formed on interlayer oxide film 130. Next, the aluminum is etched into a prescribed pattern to form aluminum interconnections 131, 132, 133, 134, 135, 136 and 137, whereby the BiCMOS circuit is completed.
According to the above-described manufacturing process of the BiCMOS circuit, however, the step of etching base electrodes 123b, 124b to form an opening reaching n type epitaxial layer 106, as shown in FIG. 39, causes p type source/drain regions 122a, 122b and n type source/drain regions 120a, 120b to be etched at the same time.
Furthermore, the step of etching the CVD oxide film to form sidewall oxide films 127a, 127b, 127c and 127d, as shown in FIG. 41, also causes p type source/drain regions 122a, 122b and n type source/drain regions 120a, 120b to be etched. As such, p type source/drain regions 122a, 122b and of n type source/drain regions 120a, 120b are subjected to etching twice, and thus surfaces thereof are scraped inevitably. This may lead to reduction in area of n type and p type wells 109 and 110 as impurity diffusion regions. As a result, there may be generated a leakage current due to unsatisfactory junction as well as variation in contact characteristics with respect to interconnections to be connected in a subsequent step.
Moreover, a large scale scraping of the surfaces of p type source/drain regions 122a, 122b and n type source/drain regions 120a, 120b due to such unnecessary etching may lead to increase in an aspect ratio of contact holes 130d, 130e, 130f and 130g for filling in the aluminum interconnections to be connected to the p type source/drain regions 122a, 122b and n type source/drain regions 120a, 120b in a subsequent step, as shown in FIG. 43. Accordingly, etching gases may not reach the bottom surfaces of contact holes 130d, 130e, 130f and 130g, i.e., p type source/drain regions 122a, 122b and n type source/drain regions 120a, 120b, thereby causing unsatisfactory etching.
An object of the present invention is to provide a semiconductor device including a BiCMOS circuit, which assures, in a step of forming a base electrode of a bipolar transistor in the BiCMOS circuit, semiconductor and contact characteristics of source/drain regions of a CMOS transistor and also allows improvement in gate resistance as well as contact characteristics of a gate electrode, and a manufacturing method thereof.
The method of manufacturing the semiconductor device according to an aspect of the present invention is specifically a method of manufacturing a semiconductor device provided with a bipolar transistor and a field effect transistor on a semiconductor substrate. The method includes the following steps.
Namely, the method of manufacturing a semiconductor device according to the present invention includes: the step of forming a first conductivity type collector region at least on the underside of a portion that is to be a first active region, the first active region being formed from the main surface of the semiconductor substrate to a prescribed depth; the step of forming an element isolating insulating film on the main surface of the semiconductor substrate to separately form, on the collector wall region, the first active region in which the bipolar transistor is to be formed, and, on a region except for that collector wall region, a second active region of a fist conductivity type in which the field effect transistor is to be formed; the step of forming first and second impurity layers of a first conductivity type in the first and second active regions, respectively; the step of forming a first insulating film on the main surface of the second active region; the step of forming a first conductive layer doped with a first conductivity type impurity on the first insulating film; the step of forming a first semiconductor layer on the main surface of the first active region and the first conductivity layer; the step of etching the first semiconductor layer, the first conductive layer, and the first insulating film to form a layer to be a base electrode on the first active region, as well as to form a gate electrode consisting of a gate electrode upper layer and a gate electrode lower layer and a gate insulating film on the second active region; the step of introducing a second conductivity type impurity into the layer to be the base electrode to form the base electrode, and introducing a second conductivity type impurity into the second active region to form a first impurity diffusion region; the step of covering with a second insulating film the gate electrode upper layer, gate electrode lower layer, gate insulating film, base electrode and first impurity diffusion region; the step of forming an opening in the second insulating film and base electrode; the step of introducing a second conductivity type impurity from the opening into the first active region to form a second impurity diffusion region to be a base region; the step of forming a sidewall insulating film on the sidewall of the opening; and the step of forming an emitter electrode in contact with the second impurity diffusion region to be fitted on the sidewall insulating film and the upper surface of the second insulating film.
According to these manufacturing steps, the base electrode and the gate electrode are formed simultaneously by etching the first semiconductor layer, the first conductive layer, and the first insulating film. Here, this etching step is conducted while the first insulating film protects the second active region. This means that the second active region that is to become the first impurity diffusion region is subjected to etching with the first insulating film as a protective film covered thereon, which can prevent excessive scraping. Similarly, the step of forming the opening in the base electrode is conducted with the presence of the second insulating film. This means that the second insulating film as a protective film protects the active region now being the first impurity diffusion region, and therefore, the surface of the first impurity diffusion region is prevented from being damaged. As a result, it becomes possible to provide a semiconductor device that can avoid degradation of semiconductor and contact characteristics due to the damage in the second active region or the first impurity diffusion region.
Preferably, in the method of manufacturing the semiconductor device according to the present invention, the step of forming the emitter electrode may include: the step of forming a second semiconductor layer having a layer to be the emitter electrode and a layer to be a resistance element, and the step of etching the second semiconductor layer to separately form the layer to be the emitter electrode and the layer to be the resistance element.
According to the above manufacturing steps, the second semiconductor layer constituting a resistance element can be formed at the same time as the formation of the layer to be an emitter electrode. As a result, it becomes possible to reduce the number of manufacturing steps in the method of manufacturing a semiconductor device including a bipolar transistor, a field effect transistor, and a resistance element on the same semiconductor substrate.
More preferably, the method of manufacturing the semiconductor device according to the present invention may further include the step of performing silicidation of the top portions of the collector region, base electrode, emitter electrode, gate electrode upper layer and the first impurity diffusion region, to form a metal silicide film.
According to the above manufacturing step, the metal silicide film is provided on the top portions of the emitter electrode, base electrode, gate electrode upper layer, and the first impurity diffusion region. Therefore, a semiconductor device allowing reduction in contact resistance when a contact interconnection is connected can be provided.
Impurity is distributed into the gate electrode upper layer by impurity diffusion from the lower layer of the gate electrode. Therefore, there is a possibility of insufficient diffusion of impurity in the gate electrode upper layer. In the absence of a metal silicide film, this may lead to increase in gate resistance in the vicinity of the upper surface of the gate electrode upper layer where the impurity is not diffused enough. According to the present manufacturing method, however, silicidation of the top of the gate electrode upper layer is achieved. The layer becomes thus conductive, whereby gate resistance of the gate electrode upper layer can be decreased. As a result, it is possible to provide a semiconductor device allowing improvement in semiconductor characteristics even when the gate electrode upper layer is formed using the step of diffusing impurity from the gate electrode lower layer to the gate electrode upper layer.
In the case the method of manufacturing the semiconductor device according to the present invention includes the step of forming a resistance element, the method includes the step of performing silicidation of the upper portions of the collector region, base electrode, emitter electrode, gate electrode upper layer and the first impurity diffusion region to form a metal silicide film, and also performing silicidation of a layer that is to become a resistance element planarly with a prescribed space to form a metal silicide film for a resistance element.
According to the above manufacturing method, it becomes possible to reduce contact resistance of a contact interconnection against the resistance element and to readily control a resistance value of the resistance element.
Furthermore, the method of manufacturing the semiconductor device according to the present invention may further include the step of forming a metal film on the base electrode and the gate electrode upper layer, instead of the above-described silicidation step.
According to the above manufacturing step, the base electrode and the gate electrode upper layer are provided with the metal film thereon. Therefore, it becomes possible to reduce possibility of generation of parasitic resistance. This parasitic resistance is generated due to the portion near the upper surface of the gate electrode upper layer where impurity is insufficiently diffused, which may cause increase in contact resistance, when a contact interconnection is connected to the gate electrode.
Preferably, the method of manufacturing the semiconductor device according to the present invention may further include the step of giving heat treatment to the gate electrode, after forming the base electrode and the gate electrode and before forming the first impurity diffusion region, to cause a first conductivity type impurity to diffuse from the gate electrode lower layer to the gate electrode upper layer.
According to the above manufacturing step, the impurity is diffused from the gate electrode lower layer to the gate electrode upper layer in the heat treatment step. As such, even when the gate electrode upper layer and the layer to be the base electrode are formed by etching and cutting out of the first semiconductor layer doped with no impurities, impurity can be diffused from the gate electrode lower layer to the gate electrode upper layer in this heat treatment step. Accordingly, it becomes possible to form a gate electrode with a prescribed impurity uniformly distributed therein, allowing reduction in the gate resistance. As a result, even when the base electrode and the gate electrode upper layer are formed in a same step by depositing the first semiconductor layer so as to reduce the number of manufacturing steps, a semiconductor device avoiding degradation in semiconductor characteristics can be provided.
The heat treatment step is conducted after etching of the first conductive layer and the first semiconductor layer is performed to isolate and form the base electrode and the gate electrode. Accordingly, the diffusion of impurity from the first conductive layer to the semiconductor layer is prevented, thereby allowing the impurity concentration of the base electrode of the bipolar transistor to be kept constant. As a result, a semiconductor device having a bipolar transistor with its semiconductor characteristics ensured can be provided.
Further, the step of heat treatment is a step normally conducted, and there is no need to add a new step of introducing an impurity into the gate electrode. Accordingly, the number of the steps as a whole is reduced.
More preferably, in the method of manufacturing the semiconductor device according to the present invention, impurity concentration of the impurity to be added to the first conductive layer to be the gate electrode lower layer is at least 1xc3x971020xc3x97{(d1+d2)/d2} cmxe2x88x923, wherein d1 designates the film thickness of gate electrode upper layer and d2 designates the film thickness of the gate electrode lower layer.
According to the above manufacturing step, the impurity concentration of the gate electrode lower layer is at least 1xc3x971020xc3x97{(d1+d2)/d2} cmxe2x88x923. This means that the amount of impurity that is introduced into the gate electrode lower layer includes the amount to be diffused into the gate electrode upper layer. Accordingly, the impurity concentration in the gate electrode as a whole is made uniform at an appropriate concentration after the impurity is diffused from the gate electrode lower layer to the gate electrode upper layer in a subsequent step of thermal diffusion. As a result, a semiconductor device allowing making small the gate resistance as well as contact resistance of the contact interconnection against the gate electrode can be provided.
More preferably, in the method of manufacturing the semiconductor device according to the present invention, the film thickness of the gate electrode lower layer is made equal to the film thickness of the gate electrode minus the film thickness of the base electrode.
According to the above manufacturing process, it becomes possible to deposit the base electrode and the first semiconductor layer to be a gate electrode upper layer in a same depositing step by adjusting in advance the film thickness of the gate electrode lower layer. Accordingly, the gate electrode and the base electrode can be formed in a single step, thereby permitting reduction in the number of manufacturing steps.
The semiconductor device according to the present invention is specifically a semiconductor device including a bipolar transistor and a field effect transistor on a semiconductor substrate. The gate electrode of the field effect transistor is formed of two layers, i.e., a gate electrode upper layer and a gate electrode lower layer, and the base electrode of the bipolar transistor and the gate electrode upper layer have the same film thickness.
To make such a structure, the above-described method of manufacturing the semiconductor device can be used. Accordingly, even when the gate electrode upper layer and the base electrode are formed from a same layer, the gate electrode and the base electrode can be formed with prescribed film thickness. As a result, the semiconductor device having this structure allows reduction in the number of manufacturing steps.
The semiconductor device according to the present invention has a feature that the gate electrode upper layer and the base electrode are both formed of a semiconductor layer doped with impurity, but having impurity concentrations different from each other.
According to the above structure, even when the base electrode and the gate electrode are formed at the same time using the above-described method of manufacturing the semiconductor device, it becomes possible to control semiconductor characteristics of the bipolar transistor and the field effect transistor.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.